1. Field of the Invention
The present invention relates in general to a fabrication method of a packaging substrate for use in circuit element packaging and a packaging method using the packaging substrate. More specifically, the present invention relates to a fabrication method of a packaging substrate where a via hole is formed in a lower surface of the substrate through an etching process to simplify the fabrication, resulting in an improved yield, and a packaging method using the packaging substrate.
2. Description of the Related Art
Technical advances in MEMS (Micro Electro Mechanical Systems) in recent years have brought the development of small, intelligent circuit elements. Before the circuits are fabricated to one single chip, they go through a ‘packaging’ process. The circuit element packaging is an encapsulation, hermetically sealing a circuit to make sure that the circuit is protected from foreign substances and external shocks, so that the circuit can maintain its high physical performance and configuration ready to be mounted on an electronic component.
For the encapsulation, a packaging substrate is prepared. The packaging substrate is then bonded with a base substrate mounted with a circuit element. In order for the circuit element to be electrically coupled to an external circuit, the packaging substrate must have an electrode that can be electrically coupled to an internal circuit.
In general, manufacturers of packaging substrates formed a via hole connecting the upper and lower surfaces of a substrate, and the via hole was usually filled with a metallic conductor by plating. The via hole was formed by etching the upper portion of the substrate, that is, the opposite side of a bonded surface with the base substrate. And a seed layer for use in plating the inside of the via hole is layered on the lower portion of the substrate. Therefore, during plating of the inside of the via hole, a plating material fills up the substrate.
After finishing the electrode fabrication, the upper surface of the substrate is planarized to be bonded evenly with the base substrate. At this time, it is very important that the plating material on the upper surface of the substrate does not escape from the via hole. Therefore, the plating process should be stopped when the electrode exposed to the upper surface of the substrate is still a little dented. This, of course, requires much attention. In addition, since the electrode, which is supposedly to be exposed to the upper surface of the substrate, is slightly dented, it is not easily visible. Thus, manufacturers have difficulty checking whether the plating operation has been properly carried out.
Meanwhile, in order to form a pad for coupling an electrode and an external terminal on the upper surface of the substrate, it is necessary to planarize the via hole portion where a plating material is not completely filled. Therefore, the upper surface of the substrate must be planarized further through the CMP (chemical-mechanical polishing) process. Unfortunately, however, there is a high probability for damage occurring to the circuit.
Typically, an electrode is made of copper (Cu) mainly because copper is easily oxidized. This means that a tremendous amount of attention is required for removing any oxidized site during the pad fabrication process. Furthermore, the surface of a packaging substrate is often cleaned prior to the circuit element packaging. Again, because of the highly oxidizable copper, there are not many options available for cleaning liquids except for organic solutions.
In the past, a photoresist film was usually used for patterning a via hole. However, the photoresist film shows poor corrosion resistance to an etching solution or etching gas, so that manufacturers had difficulty in patterning a micro-diameter via hole. Another problem with the traditional circuit element packaging was that a bonding layer had to be overlapped on the base substrate, and this layering process was rather complicated.